FANDOM


Example

DescriptionEdit

Top module.

Instantiates the Zet Core, the Wishbone Master and their communication.

InterfaceEdit

module zet (
    // Wishbone master interface
    input         wb_clk_i,
    input         wb_rst_i,
    input  [15:0] wb_dat_i,
    output [15:0] wb_dat_o,
    output [19:1] wb_adr_o,
    output        wb_we_o,
    output        wb_tga_o,  // io/mem
    output [ 1:0] wb_sel_o,
    output        wb_stb_o,
    output        wb_cyc_o,
    input         wb_ack_i,
    input         wb_tgc_i,  // intr
    output        wb_tgc_o,  // inta
    input         nmi,
    output        nmia,
 
    output [19:0] pc  // for debugging purposes
  );

As we can see, brau brau.


SignalsEdit

InputEdit

wb_clk_i: Clk signal.


wb_rst_i: Reset signal.


wb_dat_i: Data input. Connected to Wishbone master.


wb_dat_o: Data output. wb_adr_o: Address output.


wb_we_o: Write enable signal.


wb_tga_o: Select io/mem.


OutputEdit

Wires/RegsEdit

  // Net declarations
  wire [15:0] cpu_dat_o;
  wire        cpu_block;
  wire [19:0] cpu_adr_o;
 
  wire        cpu_byte_o;
  wire        cpu_mem_op;
  wire        cpu_m_io;
  wire [15:0] cpu_dat_i;
  wire        cpu_we_o;
  wire [15:0] iid_dat_i;

Instantiated ModulesEdit

Zet core

  zet_core core (
    .clk (wb_clk_i),
    .rst (wb_rst_i),
 
    .intr (wb_tgc_i),
    .inta (wb_tgc_o),
    .nmi  (nmi),
    .nmia (nmia),
 
    .cpu_adr_o  (cpu_adr_o),
    .iid_dat_i  (iid_dat_i),
    .cpu_dat_i  (cpu_dat_i),
    .cpu_dat_o  (cpu_dat_o),
    .cpu_byte_o (cpu_byte_o),
    .cpu_block  (cpu_block),
    .cpu_mem_op (cpu_mem_op),
    .cpu_m_io   (cpu_m_io),
    .cpu_we_o   (cpu_we_o),
 
    .pc (pc)
  );


Wishbone Master

zet_wb_master wb_master (
    .cpu_byte_o (cpu_byte_o),
    .cpu_memop  (cpu_mem_op),
    .cpu_m_io   (cpu_m_io),
    .cpu_adr_o  (cpu_adr_o),
    .cpu_block  (cpu_block),
    .cpu_dat_i  (cpu_dat_i),
    .cpu_dat_o  (cpu_dat_o),
    .cpu_we_o   (cpu_we_o),
 
    .wb_clk_i  (wb_clk_i),
    .wb_rst_i  (wb_rst_i),
    .wb_dat_i  (wb_dat_i),
    .wb_dat_o  (wb_dat_o),
    .wb_adr_o  (wb_adr_o),
    .wb_we_o   (wb_we_o),
    .wb_tga_o  (wb_tga_o),
    .wb_sel_o  (wb_sel_o),
    .wb_stb_o  (wb_stb_o),
    .wb_cyc_o  (wb_cyc_o),
    .wb_ack_i  (wb_ack_i)
  );

LogicEdit

 assign iid_dat_i = (wb_tgc_o | nmia) ? wb_dat_i : cpu_dat_i;


If we acknowledge an external interrupt, we blergh.